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ADE7518
8052 MCU CORE ARCHITECTURE
The ADE7518 has an 8052 MCU core and uses the 8051 instruc-
tion set. Some of the standard 8052 peripherals, such as the
UART, have been enhanced. This section describes the standard
8052 core and its enhancements used in the ADE7518.
The special function register (SFR) space is mapped into the
upper 128 bytes of internal data memory space and is accessed
by direct addressing only. It provides an interface between the
CPU and all on-chip peripherals. A block diagram showing the
programming model of the ADE7518 via the SFR area is shown
in Figure 67.
All registers except the program counter (PC), the instruction
256 BYTES
GENERAL-
PURPOSE
RAM
STACK
REGISTER
BANKS
16kB ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8051-
COMPATIBLE
CORE
PC IR
256 BYTES XRAM
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
ENERGY
MEASUREMENT
POWER
MANAGEMENT
RTC
LCD DRIVER
BATTERY
ADC
OTHER ON-CHIP
PERIPHERALS:
? SERIAL I/O
? WDT
? TIMERS
register (IR), and the four general-purpose register banks
reside in the SFR area. The SFR registers include power
control, configuration, and data registers that provide an
interface between the CPU and all on-chip peripherals.
MCU REGISTERS
The registers used by the MCU are summarized in this section.
Table 45. 8052 SFRs
Figure 67. Block Diagram
Address
0xE0
0xF0
0xD0
0x87
0x82
0x83
0x83 and 0x82
0x81
0xAF
Mnemonic
ACC
B
PSW
PCON
DPL
DPH
DPTR
SP
CFG
Bit Addressable
Yes
Yes
Yes
No
No
No
No
No
No
Description
Accumulator.
Auxiliary Math.
Program Status Word (see Table 46).
Program Control (see Table 47).
Data Pointer Low (see Table 48).
Data Pointer High (see Table 49).
Data Pointer (see Table 50).
Stack Pointer (see Table 51).
Configuration (see Table 52).
Table 46. Program Status Word SFR (PSW, 0xD0)
Bit
7
6
5
4 to 3
Address
0xD7
0xD6
0xD5
0xD4, 0xD3
Mnemonic
CY
AC
F0
RS1, RS0
Description
Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
Auxiliary Carry Flag. Modified by ADD and ADDC instructions.
General-Purpose Flag Available to the User.
Register Bank Select Bits.
RS1 RS0 Result (Selected Bank)
0 0 0
0 1 1
1 0 2
1 1 3
2
1
0
0xD2
0xD1
0xD0
OV
F1
P
Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
General-Purpose Flag Available to the User.
Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
Rev. 0 | Page 63 of 128
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